1. Field
Field effect transistor technology which may be in the form of a 3D gate (FinFET) or a planar gate MOSFET.
2. Description of the Background Art
This section describes background subject matter related to the disclosed embodiments of the present invention. There is no intention, either express or implied, that the background art discussed in this section legally constitutes prior art.
The semiconductor industry is poised to make general use of 3D FinFET gate structures and various planar MOSFET gate structures during the coming years. There is a need to develop FET gate structures which can meet the new size node in semiconductor manufacturing, which will be in the range of 10-15 nm. Because FET structures generates significant electrical effects on neighboring structures, and the spacing between the structures is decreasing, there is a need to improve the metal gate structures in a manner which better controls electrical effects while maintaining good conductivity. To provide a starting background against which the present, inventive technology may be better understood, applicants want to describe at least a portion of the published art which is related to applicants' improved metal-comprising gate structures, and a fabrication method which is useful in making the improved metal-comprising gate structures.
U.S. Pat. No. 7,105,934 to Anderson et al., issued Sep. 12, 2006, entitled: “FinFET With Low Gate Capacitance And Low Extrinsic Resistance” describes a Fin FET device designed to lower gate capacitance and extrinsic resistance in a field effect transistor. The method of forming the structure comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode and the second gate electrode. (Abstract)
U.S. Pat. No. 7,396,710 to Okuno, issued Jul. 8, 2008, entitled: “Fin-type Semiconductor Device With Low Contact Resistance And Its Manufacture Method” describes a fin-type semiconductor device which is said to have low contact resistance. The semiconductor device comprises a fin-type semiconductor region (fin) on a support substrate, where the fin has a pair of generally vertical side walls and an upper surface coupling the side walls. An insulated gate electrode structure traverses an intermediate portion of the fin, and has side walls in conformity with the side walls of the fin. (Abstract)
A U.S. Patent Application Publication of Baumgartner et al., Pub. No.: US 2009/0309162, published Dec. 17, 2009, and entitled: “Semiconductor Device Having Different Fin Widths”, describes a similar structure. The device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a different width than another fin. At least one gate is provided to control current flow through such fins. Fin spacing may be varied in addition to, or alternative to utilizing different fin widths. (Abstract)
A U.S. Patent Application Publication of Jagannathan et al., Pub. No. 2011/0260257, published Oct. 27, 2011, and entitled: “High Performance Non-Planar Semiconductor Devices With Metal Filled Inter-Fin Gaps” describes a non-planar semiconductor transistor device which includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness. A metal layer, distinct from the work-function electrode layer, covers the work function electrode layer and is arranged with a substantially uniform height with respect to the substrate, such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels. (Abstract)
U.S. Patent Application Publication of Chang et al., Pub. No. 2012/0319178, published Dec. 20, 2012, and entitled: “Double Gate Planar Field Effect Transistors” describes a stacked planar device and a method of forming the same. The method includes forming, on a substrate a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device. (Abstract)
U.S. Patent Application Publication of Wahl et al., Pub. No. 2013/0049136, published Feb. 28, 2013, and entitled: “Combined Planar FET and FIN-FET Devices and Methods” describes electronic devices having advantageous design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS). The devices are said to be obtained by providing multiple FIN-FETs and at least one planar FET on a common substrate. (Abstract)
In a paper titled: “A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts & High Density MIM Capacitors”, presented in the 2012 Symposium on VLSI Technology Digest of Technical Papers, 978-1-4673-0847-2/12 IEEE, there is a description of upcoming 22 nm logic technology. (Abstract).
While the technology discussed above has been established to work for the 22 nm node process, the next progression to a 15 nm node and further to the 11 nm node requires a change in materials and fabrication processes to accommodate the smaller size requirements while still meeting performance requirements. Requirements which must be met include trench opening size of less than 10 nm. Fin plus gate height for fill needs to be about 100 nm. This means the metal-comprising gate fill materials and processes must be applicable to a high aspect ratio trench which has an opening size in the range of 10 nm. Further, the conductivity of the gate must be maintained at a feature size of less than 10 nm. Finally, the new materials and processes must have a minimal impact on device variability. Applicants developed a significant amount of data related to resistivity of various materials as the critical dimension of a trench to be metal filled decreases from 22 nm, approaching zero. The data indicates that as the critical dimension of the metal-filled trench becomes smaller, the resistivity of a filled metal-comprising gate tends to increase exponentially. This is a serious problem which needs to be solved by a combination of specialty materials and particular fabrication techniques. The present invention relates to the solution of this problem for filled metal-comprising gates needed for the 15 nm or lower semiconductor device manufacturing node.